1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit device and a semiconductor integrated circuit device manufactured by using the same.
2. Description of the Related Art
In a semiconductor integrated circuit device, a circuit pattern is often repeatedly arranged. With a layout of the circuit patterns, constraints of the layout of the circuit patterns have been more severe, as the semiconductor fine fabrication technique proceeds. For example, in case of a DRAM, circuit patterns need to be arranged in plural times of a layout pitch of unit layout cell, depending on the size of a memory cell array. Circuits with such circuit patterns are such as a sense amplifier, a sub-word driver, a main word driver, and a Y decoder for the memory cell array. In this case, the area of the unit layout cell is determined in accordance with a circuit scale such as the width of a transistor, and the number of transistors. Areas surrounded by the broken lines in FIGS. 1A-1, 1B-1, 1C-1, 1D-1 and 1E-1 are equivalent to the areas of the unit layout cell for a transistor. However, as described later, the layout length in a pitch direction is predetermined based on the constraints. Therefore, it is necessary to elongate the unit layout cell into a height direction orthogonal to the pitch direction, in order to accommodate a conventional cell pattern.
The conventional unit layout cell pattern for a transistor will be described with reference to FIGS. 1A-1 to 1E-2. The pitch Xa of FIG. 1A-1 is the widest, and the pitches become narrower in the order of Xb of FIG. 1B-1, Xc of FIG. 1C-1, Xd of 1D-1, and Xe of FIG. 1E-1. Under the condition that the pitch is narrower than the pitch Xb of FIG. 1B-1, the unit layout cell pattern of FIGS. 1C-1, 1D-1 and 1E-1 are adopted. Which of the unit layout cell patterns of FIGS. 1C-1, 1D-1 and 1E-1 should be selected is determined based on an environment under which the unit layout cell pattern is arranged.
A layout is supposed in which a transistor with a same diffusion layer width W is repeatedly arranged within a pitch X (Xa to Xe) shown in FIGS. 1A-1 to 1E-1. In order to arrange the transistors effectively in the layout area, it is desirable to use a set of transistors. The number of transistors is determined by selecting the number of times of folding the gate electrode in accordance with the pitch.
As shown in FIGS. 2C and 2D, an array circuit 101 is connected with a memory cell array 102. The arrangement of the array circuit 101 around the memory array 102 is constrained based on the size of the memory cell array 102. For example, the area occupied by the array circuit 101 can be determined in accordance with the size of the memory cell array 102, as shown in FIG. 2C. In FIG. 2C, the array circuit 101 and the memory cell array 102 have the same length in the pitch direction. Therefore, the lengths of wiring lines, each of which connects between a corresponding one of the unit layout cells of the array circuit 101 and a corresponding portion of the memory array 102, are equal to each other, as shown in FIG. 2A-2 by arrows. Thus, signals can be uniformly propagated. On the other hand, when each of the layouts shown in FIGS. 1C-2, 1D-2, and 1E-2 can be arranged in the area of the array circuit 101 of FIG. 2C, the characteristic of this memory cell array 102 is sometimes deteriorated. This is because the layouts with smaller pitches shown in FIGS. 1D-2 and 1E-2 are arranged regardless that there is a margin in the pitch direction in relation with the memory cell array 102. At this time, the arrangement of the array circuit 101 is achieved as shown in FIG. 2D. The wiring lines, each of which connects between one unit layout cell of the array circuit 101 and a corresponding portion of the memory cell array 102, are bent as shown in FIGS. 2B-2 and 2D by the arrows. This results in non-uniform signal propagation. Therefore, in such a case, the layout of FIG. 1C-2 should be adopted.
By the way, when the source nodes of each transistor are connected with a same power supply line or a same ground line, the sources can be shared. When an output signal is outputted from each of drain nodes of the transistor, it is desirable that the drain nodes cannot be shared. In case of FIGS. 1A-2, and 1D-2, because the number of the gate electrodes extending in the height direction is even, all the source nodes can be shared, as shown by a symbol KS.
On the other hand, in case of FIG. 1B-2, because the number of the gate electrodes in the height direction is three, which is odd, the source nodes on only the one side can be made common, as shown by a symbol BS. However, as shown in a symbol BF, it is not possible to share the drain nodes. Therefore, a margin is further needed between the diffusion layers of adjacent unit layout cell patterns. That is, when one unit layout cell pattern with the gate electrodes of the odd number is repeatedly arranged, the drain nodes cannot be shared. Therefore, a field must be divided in the position shown by the symbol BF, and a space between the drain nodes or the margin between the diffusion layers becomes necessary, resulting in the decrease of layout efficiency.
As described above, when a given pitch is narrower than Xb of FIG. 1B-1 and is as much as the pitch Xc of FIG. 1C-1, a margin between the diffusion layers is insufficient in case that the number of the gate electrodes is three. Therefore, it is necessary that the number of the gate electrodes is two, as shown in FIG. 1C-1. In this case, the unit layout cell patterns of FIGS. 1D-1 and 1E-1 cannot be adopted sometimes, instead of the unit layout of FIG. 1C-1, for the reason described above. In the unit layout cell pattern of FIG. 1C-1, both sides of the diffusion layer are left as wasteful areas, and the layout area increases, compared with the case of the unit layout cell pattern of FIG. 1B-1. Also, the unit layout cell pattern of FIG. 1C-1 has a problem that the pattern height becomes high to keep the characteristic of the array circuit, compared with the unit layout cell pattern of FIG. 1B-1.
With the cell pattern repeatedly arranged, when the number of the gate electrodes in the cell pattern is odd, there is a case that the cell pattern cannot be arranged repeatedly in a predetermined field length. In such a case, the number of the gate electrodes is decreased by one such that the number of the gate electrodes is even, and then the arrangement of the cell pattern is carried out as shown in FIG. 1C-2. However, in this case, the problem of layout efficiency is not improved.
In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-163642). In the semiconductor device of this conventional example, a unit transistor pattern is repeatedly arranged such that a source, a gate, a drain, a gate are repeatedly arranged in this order, and a ground pattern is provided. All the adjacent sources of the unit transistors are connected, all the gates of the adjacent unit transistors are connected, and the drains of the unit transistors are connected.